CA3130, SCHEMATY ELEKTRONIKA, Projekty na NE555, WYKRYW.PLUSKIEW
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CA3130, CA3130A
Data Sheet
September 1998
File Number
817.4
15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
Features
• MOSFET Input Stage Provides:
- Very High Z
I
= 1.5 T
Ω
(1.5 x 10
12
Ω
) (Typ)
- Very Low I
I
. . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply terminal, an important
attribute in single-supply applications.
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (
±
2.5V to
±
8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
The CA3130A offers superior input characteristics over
those of the CA3130.
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
Pinouts
• Peak Detectors
CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW
• Single-Supply Full-Wave Precision Rectifiers
• Photo-Diode Sensor Amplifiers
OFFSET
Ordering Information
1
8
STROBE
NULL
INV.
2
7
V+
-
+
INPUT
TEMP.
RANGE
(
o
C)
NON-INV.
PART NO.
(BRAND)
PKG.
NO.
3
6
OUTPUT
INPUT
PACKAGE
V-
4
5
OFFSET
NULL
CA3130AE
-55 to 125
8 Ld PDIP
E8.3
CA3130AM
(3130A)
-55 to 125
8 Ld SOIC
M8.15
CA3130, CA3130A
(METAL CAN)
TOP VIEW
-55 to 125
8 Ld SOIC
Tape and Reel
M8.15
CA3130AM96
(3130A)
PHASE
COMPENSATION
-55 to 125
8 Pin Metal Can
T8.C
CA3130AT
TAB
STROBE
-55 to 125
8 Ld PDIP
E8.3
8
CA3130E
OFFSET
V
+
1
7
-55 to 125
8 Ld SOIC
M8.15
NULL
CA3130M
(3130)
-
+
2
6
OUTPUT
INV.
CA3130M96
(3130)
-55 to 125
8 Ld SOIC
Tape and Reel
M8.15
INPUT
3
5
OFFSET
NON-INV.
CA3130T
-55 to 125
8 Pin Metal Can
T8.C
INPUT
NULL
4
V- AND CASE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999
CA3130, CA3130A
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Metal Can Package . . . . . . . . . . . . . . . 170 85
Maximum Junction Temperature (Metal Can Package) . . . . . . .175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50
o
C to 125
o
C
NOTES:
1. Short circuit may be applied to ground or to either supply.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
CA3130
CA3130A
TEST
CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
|V
IO
|
V
S
=
±
7.5V
-
8
15
-
2
5
mV
µ
V/
o
C
Input Offset Voltage
Temperature Drift
V
IO
/
∆
T
-
10
-
-
10
-
Input Offset Current
|I
IO
|
V
S
=
±
7.5V
-
0.5
30
-
0.5
20
pA
Input Current
I
I
V
S
=
±
7.5V
-
5
50
-
5
30
pA
Large-Signal Voltage Gain
A
OL
V
O
= 10V
P-P
R
L
= 2k
Ω
50
320
-
50
320
-
kV/V
94
110
-
94
110
-
dB
Common-Mode
Rejection Ratio
CMRR
70
90
-
80
90
-
dB
Common-Mode Input
Voltage Range
V
ICR
0
-0.5 to 12
10
0
-0.5 to 12
10
V
Power-Supply
Rejection Ratio
∆
V
IO
/
∆
V
S
V
S
=
±
7.5V
-
32
320
-
32
150
µ
V/V
Maximum Output Voltage
V
OM
+
L
= 2k
Ω
12
13.3
-
12
13.3
-
V
V
OM
-
L
= 2k
Ω
-
0.002
0.01
-
0.002
0.01
V
V
OM
+
L
=
14.99
15
-
14.99
15
-
V
V
OM
-
L
=
-
0
0.01
-
0
0.01
V
Maximum Output Current
I
OM
+ (Source) at V
O
= 0V
12
22
45
12
22
45
mA
I
OM
- (Sink) at V
O
= 15V
12
20
45
12
20
45
mA
Supply Current
I+
V
O
= 7.5V,
R
L
=
-
10
15
-
10
15
mA
I+
V
O
= 0V,
R
L
=
-
2
3
-
2
3
mA
2
CA3130, CA3130A
Electrical Specifications
7.5V, T
A
= 25
o
C
Typical Values Intended Only for Design Guidance, V
SUPPLY
=
Unless Otherwise Specified
CA3130,
CA3130A
PARAMETER
SYMBOL
TEST CONDITIONS
UNITS
Input Offset Voltage Adjustment Range
10k
Ω
Across Terminals 4 and 5 or
4 and 1
22
mV
Input Resistance
R
I
1.5
T
Ω
Input Capacitance
C
I
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
e
N
BW = 0.2MHz, R
S
= 1M
Ω
(Note 3)
23
V
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability
≥
C
C
= 0
15
MHz
f
T
47pF Required.)
C
C
= 47pF
4
MHz
Slew Rate:
SR
Open Loop
C
C
= 0
30
V/
µ
s
Closed Loop
C
C
= 56pF
10
V/
µ
s
Transient Response:
C
C
= 56pF,
C
L
= 25pF,
R
L
= 2k
Ω
(Voltage Follower)
Rise Time
t
r
0.09
µ
s
Overshoot
OS
10
%
Settling Time (To <0.1%, V
IN
= 4V
P-P
)
t
S
1.2
µ
s
NOTE:
3. Although a 1M
Ω
source is used for this test, the equivalent input noise remains constant for values of R
S
up to 10M
Ω.
Electrical Specifications
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T
A
= 25
o
C
Unless Otherwise Specified (Note 4)
PARAMETER
SYMBOL
TEST CONDITIONS
CA3130
CA3130A
UNITS
Input Offset Voltage
V
IO
8
2
mV
Input Offset Current
I
IO
0.1
0.1
pA
Input Current
I
I
2
2
pA
Common-Mode Rejection Ratio
CMRR
80
90
dB
Large-Signal Voltage Gain
A
OL
V
O
= 4V
P-P
, R
L
= 5k
Ω
100
100
kV/V
100
100
dB
Common-Mode Input Voltage Range
V
ICR
0 to 2.8
0 to 2.8
V
Supply Current
I+
V
O
= 5V, R
L
=
300
300
A
V
O
= 2.5V, R
L
=
500
500
A
Power Supply Rejection Ratio
∆
V
IO
/
∆
V+
200
200
µ
V/V
NOTE:
4. Operation at 5V is not recommended for temperatures below 25
o
C.
3
CA3130, CA3130A
Schematic Diagram
“CURRENT SOURCE
LOAD” FOR Q
11
V+
CURRENT SOURCE FOR
7
BIAS CIRCUIT
Q
6
AND Q
7
Q
1
Q
2
Q
3
D
1
D
2
D
3
D
4
Z
1
8.3V
Q
4
Q
5
R
1
40k
Ω
R
2
5k
Ω
SECOND
STAGE
INPUT STAGE
D
5
D
6
D
7
D
8
(NOTE 5)
NON-INV.
INPUT
OUTPUT
STAGE
3
Q
8
+
INV.-INPUT
Q
6
Q
7
OUTPUT
2
-
6
R
3
1k
R
4
1k
Q
9
Q
10
Q
12
Q
11
R
5
1k
Ω
R
6
1k
Ω
V-
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
NOTE:
5. Diodes D
5
through D
8
provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the
output stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentially rises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g.,when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
6
, Q
7
) working into a mirror-pair of bipolar
transistors (Q
9
, Q
10
) functioning as load resistors together
with resistors R
3
through R
6
. The mirror-pair transistors also
function as a differential-to-single-ended converter to provide
base drive to the second-stage bipolar transistor (Q
11
). Offset
nulling, when desired, can be effected by connecting a
100,000
Ω
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade-connected
PMOS transistors Q
2
, Q
4
are the constant-current source for
the input stage. The biasing circuit for the constant-current
source is subsequently described. The small diodes D
5
4
CA3130, CA3130A
through D
8
provide gate-oxide protection against high-voltage
transients, including static electricity during handling for Q
6
and Q
7
.
At total supply voltages somewhat less than 8.3V, zener
diode Z
1
becomes nonconductive and the potential,
developed across series-connected R
1
, D
1
-D
4
, and Q
1
,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q
4
,Q
5
and Q
2
,Q
3
varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
V+
CA3130
7
200
A
200
A
1.35mA
8mA
(NOTE 5)
BIAS CKT.
0mA
(NOTE 7)
+
OUTPUT
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
3
A
V
≈
A
V
≈
INPUT
A
V
≈
5X
6
6000X
30X
2
-
V-
4
C
C
5
1
8
STROBE
COMPENSATION
(WHEN REQUIRED)
OFFSET
NULL
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with out-
put terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
NOTE:
8. For general information on the characteristics of CMOS transis-
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascade-connected load resistance provided by
PMOS transistors Q
3
and Q
5
. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
A
= 25
o
C
15
LOAD RESISTANCE = 5k
12.5
2k
Ω
1k
Ω
10
500
7.5
5
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
1
, diodes
D
1
through D
4
, and PMOS transistor Q
1
. A tap at the junction
of resistor R
1
and diode D
4
provides a gate-bias potential of
about 4.5V for PMOS transistors Q
4
and Q
5
with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
1
with respect to Terminal
7 to provide gate bias for PMOS transistors Q
2
and Q
3
. It
should be noted that Q
1
is “mirror-connected (see Note 8)” to
both Q
2
and Q
3
. Since transistors Q
1
,Q
2
,Q
3
are designed to
be identical, the approximately 200
2.5
0
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T
A
= 25
o
C when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T
A
=25
o
C.
A current in Q
1
establishes a similar current in Q
2
and Q
3
as constant current
sources for both the first and second amplifier stages,
respectively.
5
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CA3130, CA3130A
Data Sheet
September 1998
File Number
817.4
15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
Features
• MOSFET Input Stage Provides:
- Very High Z
I
= 1.5 T
Ω
(1.5 x 10
12
Ω
) (Typ)
- Very Low I
I
. . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply terminal, an important
attribute in single-supply applications.
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (
±
2.5V to
±
8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
The CA3130A offers superior input characteristics over
those of the CA3130.
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
Pinouts
• Peak Detectors
CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW
• Single-Supply Full-Wave Precision Rectifiers
• Photo-Diode Sensor Amplifiers
OFFSET
Ordering Information
1
8
STROBE
NULL
INV.
2
7
V+
-
+
INPUT
TEMP.
RANGE
(
o
C)
NON-INV.
PART NO.
(BRAND)
PKG.
NO.
3
6
OUTPUT
INPUT
PACKAGE
V-
4
5
OFFSET
NULL
CA3130AE
-55 to 125
8 Ld PDIP
E8.3
CA3130AM
(3130A)
-55 to 125
8 Ld SOIC
M8.15
CA3130, CA3130A
(METAL CAN)
TOP VIEW
-55 to 125
8 Ld SOIC
Tape and Reel
M8.15
CA3130AM96
(3130A)
PHASE
COMPENSATION
-55 to 125
8 Pin Metal Can
T8.C
CA3130AT
TAB
STROBE
-55 to 125
8 Ld PDIP
E8.3
8
CA3130E
OFFSET
V
+
1
7
-55 to 125
8 Ld SOIC
M8.15
NULL
CA3130M
(3130)
-
+
2
6
OUTPUT
INV.
CA3130M96
(3130)
-55 to 125
8 Ld SOIC
Tape and Reel
M8.15
INPUT
3
5
OFFSET
NON-INV.
CA3130T
-55 to 125
8 Pin Metal Can
T8.C
INPUT
NULL
4
V- AND CASE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999
CA3130, CA3130A
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Metal Can Package . . . . . . . . . . . . . . . 170 85
Maximum Junction Temperature (Metal Can Package) . . . . . . .175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50
o
C to 125
o
C
NOTES:
1. Short circuit may be applied to ground or to either supply.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
CA3130
CA3130A
TEST
CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
|V
IO
|
V
S
=
±
7.5V
-
8
15
-
2
5
mV
µ
V/
o
C
Input Offset Voltage
Temperature Drift
V
IO
/
∆
T
-
10
-
-
10
-
Input Offset Current
|I
IO
|
V
S
=
±
7.5V
-
0.5
30
-
0.5
20
pA
Input Current
I
I
V
S
=
±
7.5V
-
5
50
-
5
30
pA
Large-Signal Voltage Gain
A
OL
V
O
= 10V
P-P
R
L
= 2k
Ω
50
320
-
50
320
-
kV/V
94
110
-
94
110
-
dB
Common-Mode
Rejection Ratio
CMRR
70
90
-
80
90
-
dB
Common-Mode Input
Voltage Range
V
ICR
0
-0.5 to 12
10
0
-0.5 to 12
10
V
Power-Supply
Rejection Ratio
∆
V
IO
/
∆
V
S
V
S
=
±
7.5V
-
32
320
-
32
150
µ
V/V
Maximum Output Voltage
V
OM
+
L
= 2k
Ω
12
13.3
-
12
13.3
-
V
V
OM
-
L
= 2k
Ω
-
0.002
0.01
-
0.002
0.01
V
V
OM
+
L
=
14.99
15
-
14.99
15
-
V
V
OM
-
L
=
-
0
0.01
-
0
0.01
V
Maximum Output Current
I
OM
+ (Source) at V
O
= 0V
12
22
45
12
22
45
mA
I
OM
- (Sink) at V
O
= 15V
12
20
45
12
20
45
mA
Supply Current
I+
V
O
= 7.5V,
R
L
=
-
10
15
-
10
15
mA
I+
V
O
= 0V,
R
L
=
-
2
3
-
2
3
mA
2
CA3130, CA3130A
Electrical Specifications
7.5V, T
A
= 25
o
C
Typical Values Intended Only for Design Guidance, V
SUPPLY
=
Unless Otherwise Specified
CA3130,
CA3130A
PARAMETER
SYMBOL
TEST CONDITIONS
UNITS
Input Offset Voltage Adjustment Range
10k
Ω
Across Terminals 4 and 5 or
4 and 1
22
mV
Input Resistance
R
I
1.5
T
Ω
Input Capacitance
C
I
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
e
N
BW = 0.2MHz, R
S
= 1M
Ω
(Note 3)
23
V
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability
≥
C
C
= 0
15
MHz
f
T
47pF Required.)
C
C
= 47pF
4
MHz
Slew Rate:
SR
Open Loop
C
C
= 0
30
V/
µ
s
Closed Loop
C
C
= 56pF
10
V/
µ
s
Transient Response:
C
C
= 56pF,
C
L
= 25pF,
R
L
= 2k
Ω
(Voltage Follower)
Rise Time
t
r
0.09
µ
s
Overshoot
OS
10
%
Settling Time (To <0.1%, V
IN
= 4V
P-P
)
t
S
1.2
µ
s
NOTE:
3. Although a 1M
Ω
source is used for this test, the equivalent input noise remains constant for values of R
S
up to 10M
Ω.
Electrical Specifications
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T
A
= 25
o
C
Unless Otherwise Specified (Note 4)
PARAMETER
SYMBOL
TEST CONDITIONS
CA3130
CA3130A
UNITS
Input Offset Voltage
V
IO
8
2
mV
Input Offset Current
I
IO
0.1
0.1
pA
Input Current
I
I
2
2
pA
Common-Mode Rejection Ratio
CMRR
80
90
dB
Large-Signal Voltage Gain
A
OL
V
O
= 4V
P-P
, R
L
= 5k
Ω
100
100
kV/V
100
100
dB
Common-Mode Input Voltage Range
V
ICR
0 to 2.8
0 to 2.8
V
Supply Current
I+
V
O
= 5V, R
L
=
300
300
A
V
O
= 2.5V, R
L
=
500
500
A
Power Supply Rejection Ratio
∆
V
IO
/
∆
V+
200
200
µ
V/V
NOTE:
4. Operation at 5V is not recommended for temperatures below 25
o
C.
3
CA3130, CA3130A
Schematic Diagram
“CURRENT SOURCE
LOAD” FOR Q
11
V+
CURRENT SOURCE FOR
7
BIAS CIRCUIT
Q
6
AND Q
7
Q
1
Q
2
Q
3
D
1
D
2
D
3
D
4
Z
1
8.3V
Q
4
Q
5
R
1
40k
Ω
R
2
5k
Ω
SECOND
STAGE
INPUT STAGE
D
5
D
6
D
7
D
8
(NOTE 5)
NON-INV.
INPUT
OUTPUT
STAGE
3
Q
8
+
INV.-INPUT
Q
6
Q
7
OUTPUT
2
-
6
R
3
1k
R
4
1k
Q
9
Q
10
Q
12
Q
11
R
5
1k
Ω
R
6
1k
Ω
V-
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
NOTE:
5. Diodes D
5
through D
8
provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the
output stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentially rises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g.,when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
6
, Q
7
) working into a mirror-pair of bipolar
transistors (Q
9
, Q
10
) functioning as load resistors together
with resistors R
3
through R
6
. The mirror-pair transistors also
function as a differential-to-single-ended converter to provide
base drive to the second-stage bipolar transistor (Q
11
). Offset
nulling, when desired, can be effected by connecting a
100,000
Ω
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade-connected
PMOS transistors Q
2
, Q
4
are the constant-current source for
the input stage. The biasing circuit for the constant-current
source is subsequently described. The small diodes D
5
4
CA3130, CA3130A
through D
8
provide gate-oxide protection against high-voltage
transients, including static electricity during handling for Q
6
and Q
7
.
At total supply voltages somewhat less than 8.3V, zener
diode Z
1
becomes nonconductive and the potential,
developed across series-connected R
1
, D
1
-D
4
, and Q
1
,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q
4
,Q
5
and Q
2
,Q
3
varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
V+
CA3130
7
200
A
200
A
1.35mA
8mA
(NOTE 5)
BIAS CKT.
0mA
(NOTE 7)
+
OUTPUT
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
3
A
V
≈
A
V
≈
INPUT
A
V
≈
5X
6
6000X
30X
2
-
V-
4
C
C
5
1
8
STROBE
COMPENSATION
(WHEN REQUIRED)
OFFSET
NULL
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with out-
put terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
NOTE:
8. For general information on the characteristics of CMOS transis-
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascade-connected load resistance provided by
PMOS transistors Q
3
and Q
5
. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
A
= 25
o
C
15
LOAD RESISTANCE = 5k
12.5
2k
Ω
1k
Ω
10
500
7.5
5
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
1
, diodes
D
1
through D
4
, and PMOS transistor Q
1
. A tap at the junction
of resistor R
1
and diode D
4
provides a gate-bias potential of
about 4.5V for PMOS transistors Q
4
and Q
5
with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
1
with respect to Terminal
7 to provide gate bias for PMOS transistors Q
2
and Q
3
. It
should be noted that Q
1
is “mirror-connected (see Note 8)” to
both Q
2
and Q
3
. Since transistors Q
1
,Q
2
,Q
3
are designed to
be identical, the approximately 200
2.5
0
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T
A
= 25
o
C when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T
A
=25
o
C.
A current in Q
1
establishes a similar current in Q
2
and Q
3
as constant current
sources for both the first and second amplifier stages,
respectively.
5
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